I/O backplane controller


The SliceBus 2.0 technology was created to deliver many additional functionalities, in a price sensitive small frame.

Main Features

• Pin- and function-compatible with existing SliceBus® technology and SNAP+ ASIC

• Integrated LVDS termination resistor

• Asynchronous, serial data transmission with 192 MBit/s over Point to Point LVDS physic

• Many improved features over SNAP+ (see below in specific segments)


Basic SliceBus Information:

• Up to 64 slave (node) stations
• Additional alarm line for initialization and asynchronous event communi-cations from node to Master
• Full system detection from SliceBus Master without external information on module configuration

Error Detection Mechanism:

• CRC code with Hamming distance 4 for every telegram (all 3-bit errors are detected)
• Watchdog function inside every node for SliceBus Master observation
• “Auto shutdown” in case of SliceBus Master malfunction
• Retry statistic for early detection of possible transmission issues

Time Synchronisation

• Synchronized nanosecond clock for each node:
• Option for clock synchronization from SliceBus Master to SliceBus Master via different protocols (PROFIBUS® DP-V2,
  PROFINET®, EtherCAT®, etc.)

Technological Functions:

• Standard I/O function: 8 digital I/O or up to 32 I/O with shift register
• Integrated digital input filter function
• Asynchronous event signaling with nanosecond time stamping for ad-vanced nodes
• Two advanced counters with AB oversampling, latch, reset, output, hysteresis, compare value, repeti -tive/endless
   counting and additional time stamp information
• SSI function with time stamp information (speed calculations: counter difference/time)
• Pulse width modulation with 20 ns resolution• Frequency measurement mode
• Maximum counting frequency of 24 MHz
• Special digital I/O time stamp nodes (ETS: Edge Time Stamp System) for input edge and output control
  with nanosecond time (independent from fieldbus cycle!)

SPI Interface in NOTOS for Analog I/O / Safety / Serial CP with Exter-nal MCU

• 80-Mbit/s SPI interface for external microcontroller
• Up to 128 byte In / 128 byte Out data for external microcontroller
• Alarm function and watchdog function
• 3 additional synchronization interrupt outputs
• Channel for extended data exchange
• Extended diagnostic dataset for SPI Master

Mechanical and Electrical Specifi-cations:

• I/O voltage: 3.3V, typ. 10 mA; Core voltage: 1,2V, typ. 22 mA
• LQFP 48 package, 9.0mm², 0,5 mm pitch

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